12/01/2017 12:24
OK, it's not actually a SMPS, but similar, a 136kW LF amp. I built it
some time ago.
Having suffered with blown FET's on a 1kW 136khz Class D amplifier
since doing some circuit mods I realized the limitations of my novice
status and did some Googling. I had been looking at gate and drain
wave forms and saw nothing horrible to my eyes. I then read up on
"dead time" the time neither device should be on to stop short
circuits or over current, using two channels and two probes. This
gives the waveform attached (I hope...) and to me there doesn't seem
to be any real dead time. Is it my measurement inabilities, my
misunderstanding of dead time concepts, or have I found an issue? The
amp usually uses two paralleled FET's per "side", to minimize cost in
blown FET's I have been running just one per side. Even on reduced
voltage to the PA FET's I get one popping quite often, and I can see
no other issues, like bad antenna matching etcetera.
Where does "dead time" come from? Is it from the architecture of the
driver chips(s) itself / themselves? Or is external circuitry needed?
I see propagation delay figures cited, but I don't think this is the
same as dead time. The fact I see no dead time figures stated for
either of these IC's makes me wonder how it is created...
I put the red and blue cursors on where I expected to see the dead
time, but the switching looks instant, maybe I am not running the
scope fast enough? On the drain waveform capture I am not sure what
the blip is before the drain voltage rises. Is that some dead time, or
an attempt for both devices to conduct together?
I changed from a single dual output inverting gate driver chip type
TC4426 to two single output inverting chips type TC4452 in order to be
able to drive more powerful, higher gate capacitance MOSFET's in the
future. Maybe these have caused an issue, I had nothing like the same
failure rate before my mods.
I attach links to their data sheets and the amp's schematic. Thanks.
Basic schematic showing original single, dual output driver IC, which
seemed to be far kinder on FET's
http://www.gatesgarth.com/136bigv2mods-8.jpg
Gate driver signal capture at gates of the PA FET's, just running a
pair at 50V:
http://www.gatesgarth.com/no-dead-time.jpg
Drain pins captures:
http://www.gatesgarth.com/drain-no-dead-time3.jpg
Original dual output driver IC specs:
http://www.gatesgarth.com/TC4426.pdf
New dual driver chips, each with just a single output, much higher
current and gate capacitance ability:
http://www.gatesgarth.com/TC4452.pdf
Thanks for looking!
--
Best Regards,
Chris Wilson.
mailto: chris@chriswilson.tv
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