| To: | <amps@contesting.com> |
|---|---|
| Subject: | [Amps] FET bias |
| From: | "David Cutter" <d.cutter@ntlworld.com> |
| Date: | Mon, 24 Dec 2007 13:02:13 -0000 |
| List-post: | <mailto:amps@contesting.com> |
I have seen FET gate bias in parallel schemes isolated by a diode to each FET. This would introduce a temperature gradient seemingly counter productive to stability. Can anyone explain it? David G3UNA _______________________________________________ Amps mailing list Amps@contesting.com http://lists.contesting.com/mailman/listinfo/amps |
| <Prev in Thread] | Current Thread | [Next in Thread> |
|---|---|---|
| ||
| Previous by Date: | Re: [Amps] High voltage rectifiers for Henry 3K, George Cortez Jr |
|---|---|
| Next by Date: | [Amps] Wanted, robert perdue |
| Previous by Thread: | [Amps] High voltage rectifiers for Henry 3K, José Arturo Molina |
| Next by Thread: | Re: [Amps] FET bias, David Cutter |
| Indexes: | [Date] [Thread] [Top] [All Lists] |