Dear friends
I am trying to build a Dummy load made out of many parallel resistors (200x
10k/2W), and I am thinking of which would be the best configuration. I have
seen (and even used myself) a bus capacitor circuit with 10uF MKT caps
(power capacitor) which to enhance capacitive behaviour made a very clever
layout in which current flew in each device in the opposite direction to
cancel thier magnetic fields (and therefore reduce their stray inductance).
You can place caps on the top and the bottom and if current flows in the
opposite direction on each one at its sides and beneath it the parasitic
inductnace is reduced.
I have thought of using this idea also for the dummy load. Using to very
wide tracks on both layers and placing components on TOP and BOT layers,
where current flows in the opposit direction on each one. But which is the
minimum distance (clearance) I have to maintain between pins of opposite
voltages (for Po=400W, R=50 => V=141V). Would 5mm do it? Or even less?
I hope somebody could share his expertise with me.
Thanks in advance,
Stefan
EA5FY
_______________________________________________
Amps mailing list
Amps@contesting.com
http://lists.contesting.com/mailman/listinfo/amps
|