HENRY PFIZENMAYER wrote:
FWIW
RUN OF tentecq.SCH === SUPERSTAR === Fri Dec 24 10:20:18 2004
Freq S11 I11 A11
V11
MHz DBANG[] RECT[] RECT[]
.10000 -100.00< .0000 50.00+j.0000 .0200-j.0000 1.000
.20000 -100.00< .0000 50.00+j.0000 .0200-j.0000 1.000
.50000 -100.00< .0000 50.00+j.0000 .0200-j.0000 1.000
1.0000 -100.00< .0000 50.00+j.0000 .0200-j.0000 1.000
2.0000 -100.00< .0000 50.00+j.0000 .0200-j.0000 1.000
5.0000 -100.00< .0000 50.00+j.0000 .0200-j.0000 1.000
10.000 -100.00< .0000 50.00+j.0000 .0200-j.0000 1.000
20.000 -100.00<-.0000 50.00-j.0000 .0200+j.0000 1.000
50.000 -100.00<-.0000 50.00-j.0000 .0200+j.0000 1.000
100.00 -100.00<-.0000 50.00-j.0000 .0200+j.0000 1.000
200.00 -100.00<-.0000 50.00-j.0000 .0200+j.0000 1.000
500.00 -100.00<-.0000 50.00-j.0000 .0200+j.0000 1.000
1000.0 -100.00<-.0000 50.00-j.0000 .0200+j.0000 1.000
S11 is return loss - here greater than 100 db .
Or to most amateurs, a perfect 1:1 VSWR.
I11 is rectangular series impedance Rs , jXs
A11 is rectangular admittance - mhos - G, jB
(1/G is Rp , -1/G is Xp)
V11 is swr referred to R ( here 50 ohms reference)
__R_____C_____
| |
|__R_____L____ |
So there you have it - a parallel LC circuit that has a 1:1 VSWR all
over the band. I don't know what values you used for L and C, but it
does not matter - the result remains the same, as long as R=sqrt(L/C).
Now given the equivalent circuit of dipoles are reactances in series
with resistors, could this be exploited in any way? Perhaps making one
arm a dipole resonate above the highest frequency of interest and the
other arm a dipole resonate below the lowest frequency of interest. As
the frequency changes, so the reactance of one will become more
inductive, whereas the other will become more capacitive. Could these be
arranged to make a system that stays close to resonance? I'm 95% sure
you could force it to have two resonate frequencies, with some degree of
compensation in between those frequencies.
Merry Chrismas everyone.
David Kirkby, G8WRB.
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